In recent years, memory cells in NAND flash memories have become increasingly miniaturized. This has led to a reduction in the width of word lines for the memory cells and thus an increase in the interconnect resistance of the word lines. Thus, to reduce the interconnect resistance, much effort has been made to provide a structure that uses a metal silicide layer as an interconnect.
A select gate portion of a NAND flash memory suffers the following problem. A gate electrode in the select gate portion is silicidated. Consequently, a silicide layer contacts a gate insulating film, thus varying the threshold voltage of the select gate. Hence, various measures have been taken to prevent the silicide layer from contacting the gate insulating film. However, the increasing miniaturization of the memory cells results in formation of pinholes in a polysilicon layer. Thus, a silicide layer is formed in a part of a boundary region of a tunnel insulating film (i.e. a gate insulating film). This disadvantageously varies the threshold voltage of the select gate.